The invention relates to a circuit device for transforming a type "D" flip-flop into a flip-flop called type "B" able to sample data both on leading and trailing edges of the clock signal and comprises an exclusive OR gate whose output is electrically connected to the clock input of a type "D" flip-flop, and delay circuit means, also electrically connected with the exclusive OR gate.
As it is known, in the field of circuital components, a problem arises in using a type "D" flip-flop since it is not able to sample data at its input on both leading and trailing edges of the clock signal.
This limitation is, overcome according to a first circuit configuration in which the clock input of a type "D" flip-flop is electrically connected to the output of an exclusive OR gate, at one input of which is a delay element with which it is possible to obtain a pulse of a particular duration on the clock input of the type "D" flip-flop itself.
This delay element can be realized either by a delay line or by gates in cascade. In the first case, a rather short delay time is produced, in the second case a rather long delay time is produced.
Relative to the delay line, the delay time, value is usually known, but the procedure for obtaining it involves a very high cost not comparable with the cost of the flip-flop itself.
For rather long delay times, it is not possible to calibrate such a parameter a priori, except in a rather approximate manner, because it depends on temperature and on parameter spread of the logic components used; besides, the theoretical delay time can change only in a discrete manner according to the number of gates used in the circuit.
However, the choice of delay time value is not a negligible factor in that the qualitative performance of the flip-flop is reflected by both maximum toggle frequency and minimum pulse width.
More particularly, the correct choice of delay time value is important in that it depends on which considerations are made in order to calibrate the minimum duration of the signal to be sampled, as well as functional in performance of the flip-flop to be used. For instance, if "D" indicates the minimum duration of the signal to be sampled, it is necessary to use a flip-flop with a maximum toggle frequency greater than 2/D.
From this it follows that the ideal value of delay time is situated between the minimum pulse width and D/2.